1. Field of the Invention
The present invention relates to a probing device for measuring electrical characteristics of a test object such as a semiconductor wafer.
2. Description of the Related Art
A plurality of chips are arranged on an object, e.g., the surface of an object at regular intervals. A plurality of pads are formed at predetermined locations within the area of each chip, the pads being connected to various signal lines within the chip. The electrical characteristics of the chip are measured by putting probe needles of a testing apparatus in contact with the corresponding pads of the chip. A defective chip, if any, is identified by marking, etc. In general, the testing apparatus of this type is combined with a probe apparatus for achieving an automatic test operation.
In a probe apparatus 100, as shown in FIG. 1, a probe card 102 having probe needles arranged in accordance with the array of electrode pads of an IC chip in a wafer is situated above a wafer table 101 which is movable in X-, Y-, Z- and .theta.-directions. The probe card 102 is fixed on the lower surface of a contact ring 103 by means of, e.g. screws. The contact ring 103 is electrically connected to the probe card 102 via measuring cables or pogo pins of the contact ring 103. Further, the contact ring 103 is fixed to an insert ring 104 of the probe apparatus body by fixing means (not shown). When a probe test is performed by this probe apparatus, a test head 105 is pressed on the upper surface of the contact ring 103 such that the test head 105 is electrically connected to the contact ring 103 via the measuring cables or pogo pins. The wafer table 101 is raised to bring the probe needles into contact with the electrode pads of the chip in the wafer. In this state, electrical measurement is conducted to judge the condition of the IC chip.
Besides, recently, a multi-probe method is performed to enhance the testing efficiency. Specifically, a plurality of IC chips (e.g. 16 IC chips) are measured at a time by a probe card having probe needles corresponding to these IC chips.
In the conventional probe apparatus, however, a plurality of connection parts, such as measuring cables or pogo pins, are interposed between the IC chip to be tested and the test head, resulting in an increase in capacitance and impedance. Consequently, a high-frequency examination at 200-300 MHz or above cannot exactly be performed. In addition, it is difficult to achieve matching between the IC chip and the test head 105, and stable measurement is not surely performed.
Under the circumstances, it is thought that the probe card is directly fixed to the test head and thereby the number of connection parts is reduced to a minimum. In general, however, the test head and the probe apparatus body are mounted on separate bases, and the horizontal positions thereof are not identical. Thus, if the probe card is directly connected to the test head, the probe needles do not come into perfect contact with the IC chip even if the needles are aligned. Therefore, the horizontal plane of the probe card must be adjusted to coincide with the horizontal plane of the wafer.
In the case of the conventional probe apparatus, too, levelness adjustment is performed for the surface on which the probe card is attached and the wafer table in the process of assembling the apparatus. For example, a single probe for measuring a single chip requires a levelness of several-ten microns, and a multi-probe for measuring two or more chips at time requires an about twice higher levelness than the single probe. The weight of the test head, however, is 200 kg or more. In particular, the weight of a test head for a large-diameter wafer with high integration density is 300 to 500 kg. Furthermore, the test head is not supported by support means with high rigidity. Thus, vibration may result in misalignment. Even if high-precision level adjustment is performed at the time of assembly, desired precision may not be obtained at the time of measurement.
On the other hand, with an increase in size of a chip due to recent development of VLSI semiconductor devices, a large-size rectangular chip 51 corresponding to three consecutive chips C is formed on a silicon wafer W, as shown in FIG. 2. The chip 51 has many pads 52 for connection with bonding wires (not shown), as shown in FIG. 3. When the good/bad condition of the chip 51 is checked, the tips of needles 55 of a probe card 54 are placed under pressure on the surfaces to be tested of the pads 52 of the chip 51 placed on a table 53 having a flat upper surface, as shown in FIG. 4. Test signals are applied to the chip 51 from a circuit tester (not shown), and thereby it is checked whether the circuit construction of the chip 51 meets the design specifications. As is clear from FIG. 3, the tips of needles 55 are placed under pressure on the pads 52. However, as shown in FIG. 5, for example, in the case where the chip 51 is not parallel to the needle tips of the probe card 54, contact pressures of the right-side needle tips and left-side needle tips on the pads 52 are unbalanced. If the test signals are applied to the chip 51 from the circuit tester in this state, such test signals are not uniformly applied and the condition of the chip 51 may be misjudged.